Journal of EEIS
Current Result Document :
| 한글제목(Korean Title) |
The Impact of Delay Optimization on Delay Fault Testing Quality |
| 영문제목(English Title) |
The Impact of Delay Optimization on Delay Fault Testing Quality |
| 저자(Author) |
Young-Ho Park
Eun-Sei Park
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| 원문수록처(Citation) |
VOL 02 NO. 03 PP. 0014 ~ 0021 (1997. 06) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.
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| 키워드(Keyword) |
CAD and VLSI Design
Delay Optimization
Delay Fault Testing Quality
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| 파일첨부 |
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